Initial commit: RGB LED Strip Controller v0.3.0

- WPF + WinRT BLE controller for ELK-BLEDOM compatible LED strips

- Multi-device control, effects, grayscale and temperature modes

- Velopack updates via Gitea Releases, Gitea Actions CI

memory-bank-v2/OPERATIONS.md

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+# Memory Bank v2 Operations
+
+## Command: `update memory bank`
+
+Use this when significant changes happen or context gets stale.
+
+### Procedure
+1. Read Layer 0 (`00_project_snapshot.md`, `20_now.md`, `21_backlog.md`).
+2. Read additional Layer 1 and Layer 2 files that are relevant to touched work.
+3. Refresh core files to current truth.
+4. Write or update ADRs for durable decisions.
+5. Write a task log for significant implementation steps.
+6. Validate:
+   - All referenced ADR and task IDs exist.
+   - Core files do not contain changelog-style history.
+   - Budgets from `SCHEMA.md` are respected.
+7. Update `Last Updated` fields in touched files.
+
+### Expected Result
+- Layer 0 gives an accurate project state in minutes.
+- Decision and execution history is traceable via IDs.
+
+## Command: `compact memory bank`
+
+Use this manually for maintenance.
+
+### Triggers
+- Any file exceeds hard budget.
+- Backlog has many stale completed items.
+- Task logs older than 90 days are accumulating.
+
+### Procedure
+1. Identify oversized core files.
+2. Remove historical narrative from core files.
+3. Ensure old details live in ADR/task logs.
+4. For each month older than 90 days, create or refresh `logs/digests/YYYY-MM.md`.
+5. Replace verbose old references in core files with digest links.
+6. Re-validate ID/link integrity and budgets.
+
+### Expected Result
+- Core remains concise.
+- Older history stays discoverable through digests and linked logs.
+
+## Consistency Checklist
+- Every backlog item has an ID, status, and owner.
+- Every ADR has status (`proposed`, `accepted`, `superseded`) and links.
+- `20_now.md` and `21_backlog.md` do not conflict.
+- `00_project_snapshot.md` reflects the same priorities as `20_now.md`.